Digital Electronic Lock Circuit Diagram

This Digital Electronic Lock Circuit Diagram shown below uses 4 common logic ICs to allow controlling a relay by entering a 4 digit number on a keypad. The first 4 outputs from the CD4017 decade counter (pins 3,2,4,7) are gated together with 4 digits from a keypad so that as the keys are depressed in the correct order, the counter will advance. As each correct key is pressed, a low level appears at the output of the dual NAND gate producing a high level at the output of the 8 input NAND at pin 13.

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Digital Electronic Lock Circuit Diagram

The momentary high level from pin 13 activates a one shot circuit which applies an approximate 80 millisecond positive going pulse to the clock line (pin 14) of the decade counter which advances it one count on the rising edge.

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A second monostable, one shot circuit is used to generate an approximate 40 millisecond positive going pulse which is applied to the common point of the keypad so that the appropriate NAND gate will see two logic high levels when the correct key is pressed (one from the counter and the other from the key). The inverted clock pulse (negative going) at pin 12 of the 74C14 and the positive going keypad pulse at pin 6 are gated together using two diodes as an AND gate (shown in lower right corner).

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The output at the junction of the diodes will be positive in the event a wrong key is pressed and will reset the counter. When a correct key is pressed, outputs will be present from both monostable circuits (clock and keypad) causing the reset line to remain low and allowing the counter to advance. However, since the keypad pulse begins slightly before the clock, a 0.1uF capacitor is connected to the reset line to delay the reset until the inverted clock arrives.

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The values are not critical and various other timing schemes could be used but the clock signal should be slightly longer than the keypad pulse so that the clock signal can mask out the keypad and avoid resetting the counter in the event the clock pulse ends before the keypad pulse. The fifth output of the counter is on pin 10, so that after four correct key entries have been made, pin 10 will move to a high level and can be used to activate a relay, illuminate an LED, ect. At this point, the lock can be reset simply by pressing any key. The circuit can be extended with additional gates (one more CD4011) to accept up to a 8 digit code.

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The 4017 counting order is 3 2 4 7 10 1 5 6 9 11 so that the first 8 outputs are connected to the NAND gates and pin 9 would be used to drive the relay or light. The 4 additional NAND gate outputs would connect to the 4 remaining inputs of the CD4068 (pins 9,10,11,12). The circuit will operate from 3 to 12 volts on 4000 series CMOS but only 6 volts or less if 74HC parts are used. The circuit draws very little current (about 165 microamps) so it could be powered for several months on 4 AA batteries assuming only intermittent use of the relay.

Digital Dice With 7 Segment Display

A digital dice circuit can be easily realised using an astable oscillator circuit followed by a counter, display driver and a display. Here we have used a timer NE555 as an astable oscillator with a frequency of about 100 Hz. Decade counter IC CD4026 or CD4033 (which-ever available) can be used as counter-cum-display driver. When using CD4026, pin 14 (cascading output) is to be left unused (open), but in case of CD4033, pin 14 serves as lamp test pin and the same is to be grounded.

Circuit diagram :

Digital Dice With 7-Segment Display Circuit diagram

The circuit uses only a handful of components. Its power consumption is also quite low because of use of CMOS ICs, and hence it is well suited for battery operation. In this circuit two tactile switches S1 and S2 have been pro-vided. While switch S2 is used for initial resetting of the display to ‘0,’ depression of S1 simulates throwing of the dice by a player. 

When battery is connected to the circuit, the counter and display section around IC2 (CD4026/4033) is energised and the display would normally show ‘0’, as no clock input is available. Should the display show any other decimal digit, you may press re-set switch S2 so that display shows ‘0’. To simulate throwing of dice, the player has to press switch S1, briefly. This ex-tends the supply to the astable oscillator configured around IC1 as well as capacitor C1 (through resistor R1), which charges to the battery voltage. Thus even after switch S1 is released, the astable circuit around IC1 keeps producing the clock until capacitor C1 discharges sufficiently. Thus for du-ration of depression of switch S1 and discharge of capacitor C1 thereafter, clock pulses are produced by IC1 and applied to clock pin 1 of counter IC2, whose count advances at a frequency of 100 Hz until C1 discharges sufficiently to deactivate IC1. 

When the oscillations from IC1 stop, the last (random) count in counter IC2 can be viewed on the 7-segment display. This count would normally lie between 0 and 6, since at the leading edge of every 7th clock pulse, the counter is reset to zero. This is achieved as follows. 

Observe the behavior of ‘b’ segment output in the Table. On reset, at count 0 until count 4, the segment ‘b’ output is high. At count 5 it changes to low level and remains so during count 6. However, at start of count 7, the output goes from low to high state. A differentiated sharp high pulse through C-R combination of C4-R5 is applied to reset pin 15 of IC2 to reset the output to ‘0’ for a fraction of a pulse period (which is not visible on the 7-segment display). Thus, if the clock stops at seventh count, the display will read zero. There is a probability of one chance in seven that display would show ‘0.’ In such a situation, the concerned player is given an-other chance until the display is non-zero. 

Note.  Although it is quite feasible to inhibit display of ‘0’ and advance the counter by ‘1,’ the same makes the circuit somewhat complex and there-fore such a modification has not been attempted. 

 

 

 

Source by : Streampowers